1. Technical Field
This disclosure relates generally to video or image processing, and more specifically to methods and apparatus for processing digital video frames in block processing pipelines.
2. Description of the Related Art
Various devices including but not limited to personal computer systems, desktop computer systems, laptop and notebook computers, tablet or pad devices, digital cameras, digital video recorders, and mobile phones or smart phones may include software and/or hardware that may implement a video processing method. For example, a device may include an apparatus (e.g., an integrated circuit (IC), such as a system-on-a-chip (SOC), or a subsystem of an IC), that may receive and process digital video input from one or more sources and output the processed video frames according to one or more video processing methods. As another example, a software program may be implemented on a device that may receive and process digital video input from one or more sources and output the processed video frames according to one or more video processing methods. As an example, a video encoder 110 as shown in FIG. 1 represents an apparatus, or alternatively a software program, in which digital video input (input frames 120) is encoded or converted into another format (output frames 130), for example a compressed video format such as H.264/Advanced Video Coding (AVC) format (also referred to as MPEG 4 Part 10), according to a video encoding method. An apparatus or software program such as a video encoder 110 may include multiple functional components or units, as well as external interfaces to, for example, video input sources and external memory.
In some video processing methods, to perform the processing, each input video frame 120 is divided into rows and columns of blocks of pixels (e.g., 16×16 pixel blocks), for example as illustrated in FIG. 2 which shows an example 192×192 pixel frame 120 divided into 144 16×16 pixel blocks (illustrated in FIG. 2 as blocks 220). Each block of an input video frame 120 is processed separately, and when done the processed blocks are combined to form the output video frame 130. This may be referred to as a block processing method. Conventionally, the blocks are processed by the block processing method in scan order as shown in FIG. 2, beginning at the first block of the first row of the frame (shown as block 0), sequentially processing the blocks across the row, and continuing at the first block of the next row when a row is complete.
A block processing method may include multiple processing steps or operations that are applied sequentially to each block in a video frame. To implement such a block processing method, an apparatus or software program such as a video encoder 110 may include or implement a block processing pipeline 140. A block processing pipeline 140 may include two or more stages, with each stage implementing one or more of the steps or operations of the block processing method. FIG. 1 shows an example video encoder 110 that implements an example block processing pipeline 140 that includes at least stages 142A through 142C. A block is input to a stage 142A of the pipeline 140, processed according to the operation(s) implemented by the stage 142A, and results are output to the next stage 142B (or as final output by the last stage 142). The next stage 142B processes the block, while a next block is input to the previous stage 142A for processing. Thus, blocks move down the pipeline from stage to stage, with each stage processing one block at a time and multiple stages concurrently processing different blocks. Conventionally, the blocks are input to and processed by the block processing pipeline 140 in scan order as shown in FIG. 2. For example, in FIG. 1, the first block of the first row of the frame shown in FIG. 2 (block 0) is at stage 142C, the second block (block 1) is at stage 142B, and the third block (block 2) is at stage 142A. The next block to be input to the block processing pipeline 140 will be the fourth block in the first row.
H.264/Advanced Video Coding (AVC)
H.264/AVC (formally referred to as ITU-T Recommendation H.264, and also referred to as MPEG-4 Part 10) is a block-oriented motion-compensation-based codec standard developed by the ITU-T (International Telecommunications Union—Telecommunication Standardization Sector) Video Coding Experts Group (VCEG) together with the ISO/IEC JTCl Moving Picture Experts Group (MPEG). The H.264/AVC standard is published by ITU-T in a document titled “ITU-T Recommendation H.264: Advanced video coding for generic audiovisual services”. This document may also be referred to as the H.264 Recommendation.
Video Encoding Artifacts
Lossy video encoders typically operate on prediction pixels for the luma and chroma components of image frames, applying a transform to those prediction pixels followed by a quantization process. However, for the luma and/or chroma components of the video image frames, the quantization can translate into “blocky” artifacts and/or “color banding” artifacts. For example, it is often the case that a spatial area that contains uniform chroma values will all be quantized to the same values thus resulting in noticeable areas of color banding. Within the H.264 standard, quantization can be performed more finely in an attempt to reduce such artifacts, but this would increase the bit rate.